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| features ? 12-bit battery-cell voltage measurement ? simultaneous battery cells measurement in parallel ? cell temperature measurement ? charge balancing capability ? parallel balancing of cells possible ? integrated power supply for mcu ? undervoltage detection ? less than 10a standby current ? low cell imbalance current (< 10a) ? hot plug-in capable ? interrupt timer for cycling mcu wake-ups ? cost-efficient solution due to cost-optimized 30v cmos technology ? reliable communication between stacked ics due to level shifters with current sources and checksum monitoring of data ? daisy-chainable ? each ic monitors up to 6 battery cells ? 16 ics (96 cells) per string ? no limit on number of strings ? package qfn48 7mm 7mm applications ? battery measurement, supply and monitoring ic for li-ion and nimh battery systems in electric (ev) and hybrid electrical (hev) vehicles benefits ? highest safety level for li-ion batte ry systems in combination with ata6871 ? cost reduction due to integr ated measurement circuit and high voltage power-supply 1. description the atmel ? ata6870 is a measurement and monitoring circuit designed for li-ion and nimh multicell battery stacks in hybrid electrical vehicles. the atmel ata6870 monitors the battery-cell voltage and the battery-cell temperature with a 12-bit adc. the circuit also provides charge-balanci ng capability for each battery-cell. in addition, a linear regulator is integrated to supply a microcontroller or other external components. reliable communication between stacked ics is achieved by level-shift- ers with current sources. the atmel ata6870 can be connected to three, four, five or six battery-cells. up to 16 circuits (96 cells) can be cascaded in one string. the num- ber of strings is not limited. li-ion, nimh battery measuring, charge balancing and power-supply circuit atmel ata6870 preliminary 9116c?auto?11/10
2 9116c?auto?11/10 atmel ata6870 [preliminary] 2. block diagram figure 2-1. block diagram irq clk cell 1: reference adc cell b a l a ncing cell 6: reference adc cell b a l a ncing cell temper a t u re me asu ring mbat2 tempv ss ntc ntc av ss at s t c s _fu s e s canmode mfir s t dt s t vddfu s e vddhv avdd pow_ena vddhvm vddhvp pd_n pd_n_out temp2 mbat1 mbat7 mbat6 di s ch1 di s ch6 s ck mo s i mi s o c s _n irq_in clk_out c s _n_out s ck_out mo s i_out mi s o_in dvdd temp1 tempref gnd dv ss interchip a nd microcontroller comm u nic a tion interf a ce 3 . 3 v volt a ge reg u l a tor 3 . 3 v intern a l volt a ge reg u l a tor digit a l level s hifter te s t logic digit a l level s hifter digit a l level s hifter intern a l bi as ing to ata 6 8 70 b elow to ata 6 8 70 ab ove bia s re s s t a nd b y control mcu pwt s t 3 9116c?auto?11/10 atmel ata6870 [preliminary] 3. pin configuration figure 3-1. pinning qfn48, 7 mm 7mm atmel ata6 8 70 clk irq di s ch1 mbat2 di s ch2 mbat 3 di s ch4 di s ch5 mbat5 mbat4 di s ch 3 mbat1 at s t avdd tempv ss temp1 temp2 tempref pow_ena pd_n_out pwt s t bia s re s av ss vddhvm pd_n mi s o_in mo s i_out s ck_out c s _n_out clk_out irq_in vddhv mbat7 di s ch6 mbat6 dvdd gnd dv ss vddfu s e c s _fu s e s canmode dt s t mfir s t mi s o mo s i s ck c s _n 3 7 38 3 9 40 41 42 4 3 44 45 46 47 4 8 24 25 26 27 2 8 29 3 0 3 1 3 2 33 3 4 3 5 3 6 12 11 10 9 8 7 6 5 4 3 2 1 2 3 22 21 20 19 1 8 17 16 15 14 1 3 vddhvp table 3-1. pin description pad number pad name function remark exposed pad heatslug 1 disch5 output to drive extern al cell-balancing transistor 2 mbat5 battery cell sensing line 3 disch4 output to drive extern al cell-balancing transistor 4 mbat4 battery cell sensing line 5 disch3 output to drive extern al cell-balancing transistor 6 mbat3 battery cell sensing line 7 disch2 output to drive extern al cell-balancing transistor 8 mbat2 battery cell sensing line 9 disch1 output to drive extern al cell-balancing transistor 10 mbat1 battery cell sensing line 11 irq interrupt output for mcu/ata6870 below 12 clk system clock 13 cs_n chip select input from mcu/ata6870 below 14 sck spi clock input from mcu/ata6870 below 15 mosi master out slave in input from mcu spi data input 16 miso master in slave out output for mcu spi data output 17 mfirst select master/slave 4 9116c?auto?11/10 atmel ata6870 [preliminary] 18 dtst test-mode pin keep pin open (output) 19 scanmode test-mode pin connected to vssa 20 cs_fuse test-mode pin connected to vssa 21 vddfuse test-mode pin connected to vssa 22 dvss digital negative supply 23 dvdd digital positive supply input (3.3v) connected to avdd 24 gnd ground 25 atst test-mode pin keep pin open (output) 26 avdd 3.3v regulator output 27 avss analog negative supply 28 tempvss ground for te mperature measuring 29 temp1 temperature measuring input 1 30 temp2 temperature measuring input 2 31 tempref reference voltage for temperature measuring 32 biasres internal supply current adjustment 33 pwtst test - mode pin keep pin open (output) 34 pow_ena power regulator enable/disable 35 pd_n_out power down output 36 vddhvm power regulator output to supply e.g. an external microcontroller 37 vddhvp power regulator supply voltage 38 pd_n power down input 39 miso_in master in slave out input from ata6870 above 40 mosi_out master out slave in output for ata6870 above 41 sck_out spi clock output for input of ata6870 above 42 cs_n_out chip select output for input of ata6870 above 43 clk_out system clock output for input of ata6870 above 44 irq_in interrupt input from ata6870 above 45 vddhv supply voltage 46 mbat7 battery cell sensing line 47 disch6 output to drive external cell-balancing transistor 48 mbat6 battery cell sensing line table 3-1. pin description (continued) pad number pad name function remark 5 9116c?auto?11/10 atmel ata6870 [preliminary] 4. ata6870 system overview the atmel ? ata6870 can be stacked up to 16 times in one string. the communication with mcu is carried out on the lowest level through an spi bus. the data on the spi bus is trans- mitted to the 15 other atmel ata6870s using the communication interface implemented inside atmel ata6870. figure 4-1. battery management architecture with one battery string atmel ata 6 8 70 mcu atmel ata 6 8 70 atmel ata 6 8 70 atmel ata 6 8 70 6 9116c?auto?11/10 atmel ata6870 [preliminary] figure 4-2. battery management architecture with several battery strings mcu mcu opto to battery master controller atmel ata 6 8 70 atmel ata 6 8 70 atmel ata 6 8 70 atmel ata 6 8 70 7 9116c?auto?11/10 atmel ata6870 [preliminary] 5. absolute maximum ratings stresses beyond those listed under ?absolute maximum ratings? may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions beyond t hose indicated in the operational sections of this specification is not implied. exposure to absolute maximum rati ng conditions for extended periods may affect device reliability . unless otherwise specified all voltages to pin vssa. parameters pin symbol min. max. unit ambient temperature t a ?40 +85 c junction temperature t j ?40 +125 c storage temperature t s ?55 +150 c battery cell voltage mbat(i+1), mbat(i) v mbat(i+1) - v mbat(i) ?0.3 +5.5 v v vddhv - v vmbat7 max v vddhv - v vmbat7 ?5.5 +0.3 v v mbat1 mbat1 v mbat1 ?0.3 +0.3 v supply voltage power regulator vddhvp v vddhvp ?0.3 +33.6 v operating supply voltage vddhv v vddhv ?0.3 +30 v supply voltage dvdd (regulator is off) dvdd v dvdd ?0.3 +5.5 v supply voltage avdd (regulator is off) avdd v avdd ?0.3 +5.5 v test-input vddfuse v vddfuse ?0.3 +5.5 v reference voltage for temperature measuring (regulator is off) tempref v tempref ?0.3 vdd+0.3 v supply voltage vddhvm (regulator is off) vddhvm v vddhvm ?0.3 +5.5 v digital ground dvss v avss - v gnd ?0.3 +0.3 v analog ground avss v avss - v gnd ?0.3 +0.3 v digital/analog ground avss, dvss v avss - v dvss ?0.3 +0.3 v ground voltage for temperature measuring tempvss v tempvss ?0.3 +0.3 v input voltage for logic i/o pins clk, cs_n, sck, mosi, dtst, atst, scanmode, mfirst, pow_ena, cs_fuse, pwtst v clk , v cs_n , v sck , v mosi , v dtst , v at s t , v scanmode , v mfirst , v pow_ena , v cs_fuse , v pwtst ?0.3 vdd + 0.3 v irq, miso v irq , v miso ?0.3 +5.5 v input voltage for analog i/o pins temp1, temp2, biasres v temp1 , v temp2 , v biasres ?0.3 vdd + 0.3 v input voltage for digital high voltage input pins miso_in, irq_in v miso_in , v irq_in vddhv ? 0.3 vddhv + 0.3 v voltage at digital high voltage output pins mosi_out, sck_out, cs_n_out, clk_out v mosi_out , v sck_out , v cs_n_out , v clk_out vddhv ? 0.3 vddhv + 0.3 v input: pd_n pd_n v pd_n vddhv ? 5.5 vddhv + 0.3 v output: pd_n_out pd_n_out v pd_n_out ?5.5 +0.3 v voltage at cell balancing outputs disch(i) vdisch(i) v mbat(i) ? 0.3 v mbat(i+1) + 0.3 v 8 9116c?auto?11/10 atmel ata6870 [preliminary] hbm esd ansi/esd-stm5.1 jesd22-a114 aec-q100 (002) esd 2 kv cdm esd stm 5.3.1 500 v 1, 12, 13, 24, 25, 36, 37, 48 750 v latch-up acc. to aecq100-004, jesd78a latch-up 100 ma 5. absolute maximum ratings (continued) stresses beyond those listed under ?absolute maximum ratings? may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions beyond t hose indicated in the operational sections of this specification is not implied. exposure to absolute maximum rati ng conditions for extended periods may affect device reliability . unless otherwise specified all voltages to pin vssa. parameters pin symbol min. max. unit 6. thermal resistance parameters symbol value unit package. qfn48 7 7 max. thermal resistance junction-ambient (1) r thja max 20 k/w max. thermal resistance junction-case r thjc max tbd k/w note: 1. package mounted on 4 large pcb (per jesd51- 7) under natural convention as defined in jesd51-2. 9 9116c?auto?11/10 atmel ata6870 [preliminary] 7. circuit description and electrical characteristics unless otherwise specified all parameters in this section are valid for a supply voltage range of 6.9v < v ddhv < 30v and a battery cell voltage of v mbat(i+1) ? v mbat(i) =0v to 5v, ?40c < t a < 85c. all values refe r to pin vssa, unless otherwise specified. 7.1 operating modes the ata6870 has two operation modes. 1. power-down mode (pdmode) 2. normal mode (norm mode) 7.1.1 power-down mode in power-down mode all blocks of the ic are switched off. the circuit can be switched from power-down to on mode or back via the pd_n input. if the pin is connected to vddhv via an external opto coupler, for example, the circuit is in on mode. if several atmel ? ata6870 are stacked, the power- down signal must be only provided for the ic on the top level of the stack. the next lower ic receives this information from the pd_n_out output of its upper ic. the pd_n_out pin must be connected to either the pd_n pin of the next lower atmel ata6870 or to vssa. 10 9116c?auto?11/10 atmel ata6870 [preliminary] figure 7-1. power-down s canmode c s _fu s e dt s t dv ss av ss at s t vddfu s e gnd irq clk cell 1: reference adc cell b a l a ncing cell 6: reference adc cell b a l a ncing cell temper a t u re me asu ring mbat2 tempv ss ntc ntc s canmode c s _fu s e dt s t dv ss av ss at s t mfir s t mfir s t vddfu s e vddhv avdd pow_ena vddhvm vddhvp pd_n pd_n_out temp2 mbat1 mbat7 mbat6 di s ch1 di s ch6 s ck mo s i mi s o c s _n irq_in clk_out c s _n_out s ck_out mo s i_out mi s o_in dvdd temp1 tempref interchip a nd microcontroller comm u nic a tion interf a ce 3 . 3 v volt a ge reg u l a tor 3 . 3 v intern a l volt a ge reg u l a tor digit a l level s hifter te s t logic digit a l level s hifter digit a l level s hifter intern a l bi as ing ata6 8 70 ata6 8 70 bia s re s s t a nd b y control gnd irq clk cell 1: reference adc cell b a l a ncing cell 6: reference adc cell b a l a ncing cell temper a t u re me asu ring mbat2 tempv ss ntc ntc vddhv avdd pow_ena vddhvm vddhvp pd_n pd_n_out temp2 mbat1 mbat7 mbat6 di s ch1 di s ch6 s ck mo s i mi s o c s _n irq_in clk_out c s _n_out s ck_out mo s i_out mi s o_in dvdd temp1 tempref interchip a nd microcontroller comm u nic a tion interf a ce 3 . 3 v volt a ge reg u l a tor 3 . 3 v intern a l volt a ge reg u l a tor digit a l level s hifter te s t logic digit a l level s hifter digit a l level s hifter intern a l bi as ing bia s re s s t a nd b y control mcu pwt s t pwt s t 11 9116c?auto?11/10 atmel ata6870 [preliminary] 7.1.2 normal operating mode (norm mode) the atmel ? ata6870 turns on when the pd_n signal is switched from low to high. the power supplies avdd and dvdd as well as vddhvm (if the input signal pow_ena = high) are turned on. the configuration registers are set to their default values. in norm mode the atmel ata6870 can acquire analog data (voltage or temperature channels) upon request from the host microcontroller. when the host microcontroller orders an acquisition through the spi bus, the ic starts digitizing all voltage and one temperature channel in parallel. the on-chip digital signal processor filters, in real time, the channel samples. when conversion and filtering are done, the data-ready interrupt to the host processor indicates the data availability. the mcu can now read the adc result registers. the mcu reads the atmel ata6870?s status registers to check each ic and to acknowledge the interrupt. when atmel ata6870 is in norm mode, the mcu can be active or in idle mode. in order to wake-up the mcu by an interrupt, the low frequency timer (lft) can be activated in atmel ata6870. interrupt is signaled with a high level on irq pin. the lft is re-programmable on the fly and can be reset through spi, but is not stoppable. figure 7-2. atmel ata6870 in norm mode table 7-1. electrical characteristics no. parameters test conditions pi n symbol min. typ. max. unit type* 1.1 maximum allowed input current in power-down mode (e.g., leakage current of an optocoupler) pd_n i pd_n 50 a a 1.2 input current in on mode pd_n i pd_n 2.5 5 ma a 1.3 maximum voltage (pin pd_n left open) i pd_n = 0 to 50a pd_n v vddhv - v pd_n 5va 1.4 propagation delay time from power-down mode to norm mode min slope dvdd t vddon 3msa 1.5 propagation delay time from norm mode to power-down mode dvdd t vddoff 10 ms a *) type means: a = 100% tested, b = 100% correlation tested, c = characterized on samples, d = design parameter i pd_n 1 ma msec ------------- - = b a ckgro u nd t as k/idle b a ckgro u nd t as k s end s pi comm a nd b a ckgro u nd t as k interr u pt h a ndling re a d s t a t us regi s ter acq cmd a ss erted idle idle ac qu i s ition a s ic s in nomode mcu s pi irq re a d d a t a bu r s t mode proce ss ing 12 9116c?auto?11/10 atmel ata6870 [preliminary] 7.2 interface to battery cells each input line mbat(i) and the supply lines vddhv, avss can be pr otected by additional resistors and a filter capacitor as shown below. figure 7-3. external components between atmel ? ata6870 and the battery cells mbat (i) are high impedance input (~2 m ). thus, external components can be added to pro- tect ata6870 chip against current spikes and overvoltage at battery cell level. table 7-2. electrical characteristics no. parameters test conditions pi n symbol min. typ. max. unit type* 2.1 supply voltage vddhv v vddhv 6.9 30 v a 2.2 current consumption ivddhv (normal mode) vddhv i vddhv 15 ma a 2.3 current consumption in power-down mode (pdmode) i vddhv + i mbat(i) max (1) v mbat(i+1) ? v mbat(i) = 3.7v vddhv 10 a a 2.4 imbalance from battery cell to battery cell in power-down mode (pdn mode) v mbat(i+1) ? v mbat(i) = 3.7v mbat(i+1) i mbat(i+1) 10 a a *) type means: a = 100% tested, b = 100% correlation tested, c = characterized on samples, d = design parameter note: 1. largest input current of the cell inputs mbat(i) mbat(i+1) r_in r_in b a ttery cell(i) bo a rd b a ttery cell ata6 8 70 cell(i) di s ch(i) av ss di s ch a rge re s i s tor r_vddhv r_v ss vddhv mbat(i) 13 9116c?auto?11/10 atmel ata6870 [preliminary] 7.3 reduced number of batt ery cells configuration it is possible for atmel ? ata6870 to operate with a reduced number of cells: 3, 4, 5, and 6 cell operation are possible. in these cases, the cell-chip inputs corresponding to the missing cells should be connected to the upper cell potential of the module. figure 7-4. connection with 4 cells only battery cell 1 (mbat1, mbat2) and battery cell 6 (mbat6, mbat7) must always be used for the lowest/highest cell. table 7-3. electrical characteristics no. parameters test conditions pi n symbol min. typ. max. unit type* 3.1 r_in mbat(i) 1 k d 3.2 r_vddhv vddhv 50 d 3.3 r_vss avss 50 d *) type means: a = 100% tested, b = 100% correlation tested, c = characterized on samples, d = design parameter mbat6 atmel ata6 8 70 di s ch5 mbat4 mbat5 di s ch4 pow_ena vddhvp vddhvm c s _n_out clk_out s ck_out mo s i_out irq pd_n_out pd_n clk c s _n s ck mo s i mi s o irq_in mi s o_in bia s re s dvdd avdd mbat7 di s ch6 di s ch 3 mbat 3 mbat2 di s ch1 mbat1 gnd di s ch2 tempref temp2 temp1 tempv ss av ss vddhv dv ss dt s t c s _fu s e s canmode at s t vddfu s e mfir s t 14 9116c?auto?11/10 atmel ata6870 [preliminary] 7.4 ata6870 external mcu supply the atmel ? ata6870 provides a 3.3v power-supply for external components such as the microcontroller unit (mcu). the input pin for this supply is pin vddhvp, and the output pin is vddhvm. this regulator is able to supply the mcu directly from the topmost battery cell of a string. the power regulators of all stacked atmel ata6870 are therefore put in serial configu- ration to avoid imbalance.the regulator can be disabled with the digital input pin pow_ena. logic levels: low = v dvss , high = v dvdd table 7-4. truth table pin symbol value function pow_ena v pow_ena low voltage regulator disabled high voltage regulator enabled 15 9116c?auto?11/10 atmel ata6870 [preliminary] figure 7-5. mcu supply with the inte rnal power supply s canmode c s _fu s e dt s t dv ss av ss at s t vddfu s e gnd irq + + clk cell 1: reference adc cell b a l a ncing cell 6: reference adc cell b a l a ncing cell temper a t u re me asu ring mbat2 tempv ss s canmode c s _fu s e dt s t dv ss av ss at s t mfir s t mfir s t vddfu s e vddhv avdd pow_ena vddhvm vddhvp pd_n pd_n_out temp2 mbat1 mbat7 mbat6 di s ch1 di s ch6 s ck mo s i mi s o c s _n irq_in clk_out c s _n_out s ck_out mo s i_out mi s o_in dvdd temp1 tempref interchip a nd microcontroller comm u nic a tion interf a ce 3 . 3 v volt a ge reg u l a tor 3 . 3 v intern a l volt a ge reg u l a tor digit a l level s hifter te s t logic digit a l level s hifter digit a l level s hifter intern a l bi as ing ata6 8 70 ata6 8 70 bia s re s s t a nd b y control gnd irq clk cell 1: reference adc cell b a l a ncing cell 6: reference adc cell b a l a ncing cell temper a t u re me asu ring mbat2 tempv ss vddhv avdd pow_ena vddhvm vddhvp pd_n pd_n_out temp2 mbat1 mbat7 mbat6 di s ch2 di s ch6 s ck mo s i mi s o c s _n irq_in clk_out c s _n_out s ck_out mo s i_out mi s o_in dvdd temp1 tempref interchip a nd microcontroller comm u nic a tion interf a ce 3 . 3 v volt a ge reg u l a tor 3 . 3 v intern a l volt a ge reg u l a tor digit a l level s hifter te s t logic digit a l level s hifter digit a l level s hifter intern a l bi as ing bia s re s s t a nd b y control mcu pwt s t pwt s t 16 9116c?auto?11/10 atmel ata6870 [preliminary] table 7-5. electrical characteristics no. parameters test conditions pin symbol min. typ. max. unit type* 4.1 supply voltage vddhvp v vddhvp 6.9 33.3 v a 4.2 output voltage vddhvm v vddhvm 3.1 3.3 3.5 v a 4.3 dc output current vddhvm i vddhvm 20 ma a 4.4 peak output current (1) vddhvm i vddhvm 50 ma a 4.5 capacitor load (2) vddhvm 30 33 f d 4.6 capacitor load (2) vddhvm 200 220 nf d 4.7 high level input voltage pow_ena v pow_ena 0.7 v dvdd va 4.8 low level input voltage pow_ena v pow_ena 0.3 v dvdd va 4.9 hysteresis pow_ena v pow_ena 0.05 v dvdd vc 4.10 input current v pow_ena =0v to v dvdd pow_ena i pow_ena ?1 +1 a a *) type means: a = 100% tested, b = 100% correlation te sted, c = characterized on samples, d = design parameter notes: 1. maximum current the power regulator can prov ide, time limited by thermal consideration only 2. these capacitors are mandatory 17 9116c?auto?11/10 atmel ata6870 [preliminary] figure 7-6. mcu supply with an exte rnal power supply s canmode c s _fu s e dt s t dv ss av ss at s t vddfu s e gnd irq clk cell 1: reference adc cell b a l a ncing cell 6: reference adc cell b a l a ncing cell temper a t u re me asu ring mbat2 tempv ss s canmode c s _fu s e dt s t dv ss av ss at s t mfir s t mfir s t vddfu s e vddhv avdd pow_ena vddhvm vddhvp pd_n pd_n_out temp2 mbat1 mbat7 mbat6 di s ch2 di s ch6 s ck mo s i mi s o c s _n irq_in clk_out c s _n_out s ck_out mo s i_out mi s o_in dvdd temp1 tempref interchip a nd microcontroller comm u nic a tion interf a ce 3 . 3 v volt a ge reg u l a tor 3 . 3 v intern a l volt a ge reg u l a tor digit a l level s hifter te s t logic digit a l level s hifter digit a l level s hifter intern a l bi as ing ata6 8 70 ata6 8 70 bia s re s s t a nd b y control gnd irq clk cell 1: reference adc cell b a l a ncing cell 6: reference adc cell b a l a ncing cell temper a t u re me asu ring mbat2 tempv ss vddhv avdd pow_ena vddhvm vddhvp pd_n pd_n_out temp2 mbat1 mbat7 mbat6 di s ch2 di s ch6 s ck mo s i mi s o c s _n irq_in clk_out c s _n_out s ck_out mo s i_out mi s o_in dvdd temp1 tempref interchip a nd microcontroller comm u nic a tion interf a ce 3 . 3 v volt a ge reg u l a tor 3 . 3 v intern a l volt a ge reg u l a tor digit a l level s hifter te s t logic digit a l level s hifter digit a l level s hifter intern a l bi as ing bia s re s s t a nd b y control mcu pwt s t pwt s t 18 9116c?auto?11/10 atmel ata6870 [preliminary] 7.5 analog blocks 7.5.1 battery voltage measuring figure 7-7. block diagram battery voltage measurement the battery voltage measurement block contains ? a 2-input multiplexer ? a voltage reference, ?a 12-bit adc ? the upper part of digital voltage level shifters 7.5.1.1 input multiplexer the multiplexer has 3 inputs. each of the functions are described in the table below: the multiplexer inputs are controlled by spi. 12 b it s increment a l adc mbat(i+1) di s ch(i) mbat(i) bit s tre a m dvdd di s ch(i) dv ss mux clk high volt a ge level s hifter (digit a l) 1.666v reference external ata6 8 70 cell i table 7-6. inputs of the multiplexer input function v(mbat (i+1) , mbat (i) ) input voltage measurement v(mbat (i) , mbat (i) ) offset error acquisition of adc 19 9116c?auto?11/10 atmel ata6870 [preliminary] 7.5.1.2 12 bits incremental adc the purpose of this cell is to convert an analog input into a 12-bit digital word. table 7-7. electrical characteristics no. parameters test conditions pin symbol min. typ. max. unit type* 5.1 accuracy of voltage channel (1) maximum input noise 0.5mvrms 2.2v < v mbat(i+1) ? v mbat(i) <4.5v mbat(i+1), mbat(i) ?10 +10 mv a maximum input noise 0.5mvrms 0v < v mbat(i+1) ? v mbat(i) <5v mbat(i+1), mbat(i) ?20 +20 mv a 5.2 accuracy of voltage channel (1)(2) maximum input noise 0.5mvrms v mbat(i+1) ? v mbat(i) = 3.7v mbat(i+1), mbat(i) ?7 +7 mv a 5.3 input voltage range mbat(i+1), mbat(i) v mbat(i+1) , v mbat(i) 05va 5.4 input resolution (1 lsb) v lsb 1.5 mv d 5.5 reference voltage v ref 1.667 v d 5.6 offset voltage mbat(i+1), mbat(i) v mbat(i+1) , v mbat(i) 410 lsb a 5.7 gain voltage mbat(i+1), mbat(i) v mbat(i+1) , v mbat(i) 655 lsb/v a 5.8 system clock clk f clk 450 500 550 khz d 5.9 spi interface clock sck f sck 0.5 f clk d 5.10 conversion rate (3) t conv = (2 12 + 1) / f clk t conv 8.194 ms d 5.11 input bandwidth mbat(i+1), mbat(i) f bw 50 hz d *) type means: a = 100% tested, b = 100% correlation te sted, c = characterized on samples, d = design parameter notes: 1. the accuracy of the voltage channels is guaranteed with no external resistor in the mbat(i), mbat(i+1) lines. 2. reduced temperature range (?20c to + 65c) 3. conversion rate without readout times of spi 20 9116c?auto?11/10 atmel ata6870 [preliminary] converting adc resu lts to voltage the silicon is factory adjusted by measuring offset voltage (v offset) with both adc inputs con- nected to mbati and calibration of the adc(mbat i+1 ) value to 3031 at mbat i+1 =4.0v (see figure 7-8 ). figure 7-8. characteristics of ad-converter adc(voffset): adc result with both adc inputs connected to mbat i (0v input voltage) adc(vmbat i+1 -vmbat i ): uncorrected adc result of the adc input voltage standard procedure with frequent offset adjustment to use the possibility of frequent ly offset adjustment of the ad c the following parameters have to be measured: adc(voffset) adc result with both adc inputs connected to mbat i (0v input voltage) adc(vmbat i+1 -vmbat i ) uncorrected adc result of the adc input voltage calculation of the battery cell voltage: vin = 4v (adc(vmbat i+1 -vmbat i ) ? adc(voffset)) / (3031 ? adc(voffset)) with vin = v(mbat i+1 )-v(mbat i ) measuring of voffset must not be done at every measuring cycle. frequently updates are sufficient. standard procedure without offset adjustment with increasing input voltages the failure caus ed by the adc can be neglected. in this case the battery cell voltage can be calculated by the following equation: vin = 4v (adc(vmbat i+1 -vmbat i ) ? 0.1 2 12 ) / (3031 ? 0.1 2 12 ) the following simplification can be done with less than 1mv rounding error: vin = 1.52656 10 -3 (adc(vmbat i+1 -vmbat i ) ? 410) 410 d = 0.1 * 2 12 3 6 8 6 d = 0.9 d * 2 12 s lope = ( 3 0 3 1 - 410 d )/4v = 655 d l s b/v inp u t volt a ge (mbat i+1 , mbat i ) 0 5 0 adc o u tp u t 3 0 3 1 4 21 9116c?auto?11/10 atmel ata6870 [preliminary] 7.5.1.3 acquisition time and clocking the acquisition time depends on the number of atmel ? ata6870s to be addressed. spi clock (pin sck) must a maximum of half the frequency of the system clock clk. table 7-8. electrical characteristics number of ata6870 sck frequency (khz) clk frequency (khz) conversion time (ms) total acquisition duration (ms) (1) 1 250 500 8.2 9.5 2 250 500 8.2 10.2 3 250 500 8.2 10.8 4 250 500 8.2 11.5 5 250 500 8.2 12.2 6 125 500 8.2 17.0 7 125 500 8.2 18.4 8 125 500 8.2 19.7 9 125 500 8.2 21.1 10 62.5 500 8.2 36.1 11 62.5 500 8.2 38.8 12 62.5 500 8.2 41.5 13 62.5 500 8.2 44.2 14 62.5 500 8.2 46.8 15 62.5 500 8.2 49.5 16 62.5 500 8.2 52.2 notes: 1. the total acquisition time takes the following into account: - adc conversion - reading of voltage values in burst mode for all ata6870 devices, - reading of temperature values for all ata 6870 devices (only one temperature input is read). 22 9116c?auto?11/10 atmel ata6870 [preliminary] 7.5.2 battery cell discharge each battery cell can be discharged with an external resistor and an nmos transistor. figure 7-9. external circuit for cell balancing the pin disch(i) (discharge for battery cell i) is intended to switch on the external discharge resistor in parallel to the battery cell to bypass charge current for cell balancing reasons. the pin disch(i) is a digital output: no discharge: v disch(i) = v mbat(i) discharge: v disch(i) = v mbat(i+1) mbat(i+1) r_in r_in b a ttery cell(i) bo a rd b a ttery cell ata6 8 70 cell(i) di s ch(i) av ss di s ch a rge re s i s tor r_vddhv r_v ss vddhv mbat(i) table 7-9. electrical characteristics no. parameters test conditions pi n symbol min. typ. max. unit type* 6.1 operating voltage range mbat(i) mbat (i+1) ? mbat (i) 1.5 5 v a 6.2 high-level output voltage i disch(i) = ?10a, mbat (i+1) ? mbat (i) = 1.5v to 5v disch(i) v disch(i) ? v mbat(i) v mbat(i+1) ? 50 mv va 6.3 high-level output voltage i disch(i) = ?1ma mbat (i+1) ? mbat (i) = 3v to 5v disch(i) v disch(i) ? v mbat(i) v mbat(i+1) ? 0.6v va 6.4 pull-down resistor (1) disch(i)- mbat(i) 60 140 k a *) type means: a = 100% tested, b = 100% correlation te sted, c = characterized on samples, d = design parameter note: 1. integrated pull-down resistor between pins disch(i) and mbat(i) 23 9116c?auto?11/10 atmel ata6870 [preliminary] 7.5.3 temperature channel the temperature sensors are based on a resistor divider using a standard resistor and an ntc resistor. this resistor divider is connected to the reference of the adc for temperature mea- suring. as the adc is sharing same reference value, the output of temperature measurement with adc is ratio metric. figure 7-10. battery cell temperature measurement during one measuring cycle only one temperature input can be measured by the adc. the channel can be selected in the operation register (0x02) by the tempmode bit (bit 3). the adc output is equal to: tempv ss 12 b it s increment a l adc 1.2v reference temp1 re s _ntc2 re s _ref2 temp2 avdd tempref out oper a tion regi s ter re s _ref1 re s _ntc1 out 2048 1 res_ntc(1) (res_ntc(1) + res_ref(1)) -------------------------------------------------------------------------------- - 8 15 ------ 8 10 ------ ? + ?? ?? = table 7-10. electrical characteristics no. parameters test conditions pin symbol min. typ. max. unit type* 7.1 reference voltage tempref v tempref ? v tempvss 1.1 1.2 1.3 v a 7.2 reference voltage output current tempref i tempref 2maa 7.3 input voltage range temp1 v temp1 0v tempref va 7.4 input voltage range temp2 v temp2 0v tempref va 7.5 input current vtempx = 1.2v tempx i tempx 1aa 7.6 code output for value(res_ntcx) = value (res_refx) v(tempi, tempvss) = 0.5 v(tempref, tempvss) 931 d 956 d 981 d a 7.7 code output for value(res_ntc) = 0 v(tempi, tempvss) = 0 385 d 410 d 435 d a 7.8 code output for value(res_ntc) = infinite v(tempi, tempvss) = v(tempref) 1477 d 1502 d 1527 d a *) type means: a = 100% tested, b = 100% correlation te sted, c = characterized on samples, d = design parameter 24 9116c?auto?11/10 atmel ata6870 [preliminary] 7.5.4 internal voltage regulator the regulator output is pin avdd. the pins avdd and dvdd have to be connected together. an external filtering ca pacitor (10nf recomm ended) is used to filter and stabilize the function. the regulator output can be used to supply outside functions at the price of power supply imbalance between battery cells. 7.5.5 central biasing this block generates a precise bias current to supply internal blocks of the ic. connection of any external loads to this pin is not allowed. figure 7-11. internal bias current generation table 7-11. electrical characteristics no. parameters test conditions pin symbol min. typ. max. unit type* 8.1 supply voltage range vddhv v vddhv 6.9 30 v a 8.2 regulated output voltage avdd v avdd 3.1 3.3 3.5 v a 8.3 output current avdd i avdd 05maa 8.4 c load (load capacitor) c load 910 nfd *) type means: a = 100% tested, b = 100% correlation te sted, c = characterized on samples, d = design parameter table 7-12. electrical characteristics no. parameters test conditions pin symbol min. typ. max. unit type* 9.1 biasing voltage biasres v biasres 1.2 v a 9.2 external resistor r refbias 121 k d 9.3 tolerance r refbias ?1 +1 % d 9.4 maximum external parasitic capacitor biasres c external 50 pf d *) type means: a = 100% tested, b = 100% correlation te sted, c = characterized on samples, d = design parameter bia s re s 121 k b a ndg a p 1.2v i bia s r refbia s 25 9116c?auto?11/10 atmel ata6870 [preliminary] 7.5.6 rc oscillator 7.5.7 power on reset the power on reset is used to initialize the digital part at power-up. the power on reset circuit is functional when the voltage at pin dvdd is larger than v porop . there are two reset sources: system ?hard reset? system hard reset occurs when the voltage at pin dvvd goes below the power on reset threshold. ata6870 registers are set to their initial values. after t = t reset , the mcu can access the atmel ? ata6870. figure 7-12. power on reset table 7-13. internal rc osc illator frequency no. parameters test conditions pin symbol min. typ. max. unit type* 10.1 oscillator frequency f osc 45 50 55 khz a *) type means: a = 100% tested, b = 100% correlation te sted, c = characterized on samples, d = design parameter v dvdd v por v porop v poron v poroff table 7-14. electrical characteristics no. parameters test conditions pin symbol min. typ. max. unit type* 11.1 power on reset functional dvdd v porop 0.8 v a 11.2 power on reset off dvdd v poroff 1.5 2.5 v a 11.3 power on reset hysteresis dvdd v poroff ? v poron 0.03 v c 11.4 power on reset time t reset 800 s a *) type means: a = 100% tested, b = 100% correlation te sted, c = characterized on samples, d = design parameter 26 9116c?auto?11/10 atmel ata6870 [preliminary] 7.6 digital part 7.6.1 general features the digital parts of the ata6870 includes the following blocks: ? 4-wire-spi full duplex communication with external host mcu ? spi system protocol management (frames decoding) and configuration registers bank ? interrupt to mcu management ? operations decoding (voltage and/or temperature acquisition) and analog part control ? low frequency timer (50khz) for wake-up management 7.6.2 host interface figure 7-13. host interface the communication between atmel ? ata6870 (1) and its host mcu, as well as ata6870 (n) and ata6870(n-1) is based on a 4 wire serial/par allel spi interface (cs_n, sck, miso, mosi) and an interrupt line (irq). the spi interface allows register read and write operations. the interrupt line indicates events that require host intervention. atmel ata6870(n)?s 4 wire-spi bus inputs (c s_n, sck, mosi) are up-shifted through level shifters. they are internally connected to the outputs cs_n_out, sck_out, mosi_out and connected to ata6870(n+1) (cs_n, sck, mosi). atmel ata6870(n)?s 4 wire-spi bus output (miso) and ata6870(n)?s interrupt (irq) are down-shifted through level shifters and connected to ata6870(n-1) (mosi_in, irq_in) or host mcu (n = 1). s pi ata6 8 70 (1) s pi s l a ve s pi m as ter mcu c s _n mfir s t mi s o irq mo s i s ck vdd microcontroller unit v dvdd 27 9116c?auto?11/10 atmel ata6870 [preliminary] 7.6.3 interrupt in norm mode (normal mode), the reasons for an interrupt request are: ? the availability of meas ured data (data ready) when a voltage measurement is completed, the datardy flag is set in the status register. the ata6870 cannot decode any new incoming operation until the datardy flag is released. ? the low frequency timer (lft) elapses (wakeup) the wakeup flag is set in the status register when the lft elapses. the lft is controlled via the spi interface. ? a transmission error is flagged during the last spi transaction (the commerror bit is set in the status register). ? if an undervoltage condition occurs. the undervoltage function is controllable via spi interface. a mask bit in the irqmask register corresponds to each interrupt source. the mcu must read the ata6870 status register before the interrupt is cleared. with each spi access a 16-bit irq state is sent via miso to the mcu with the interrupt state of all stacked ata6870 (see section 7.6.4.1 ?spi transaction fields? on page 27 ). in pdmode (power down), if the digital control part and mcu are not supplied, neither spi command nor interrupt are transmitted over the interface. 7.6.4 spi interface the full duplex spi interface block allows co mmunication with the host mcu using four wires (miso, mosi, sck and cs_n). spi transacti ons are based on a byte-access msb first protocol. 7.6.4.1 spi transaction fields most of the time, the spi frame is defined by 4 distinct fields: identification (2 bytes): 16-b it chip identification (mosi) , in parallel 16-bit irq state (miso) control (1 byte): 7-bit register address + 1-bit read/write information (mosi) data (k byte): k*8 bits data (mosi or miso depending on the access direction) chksum (1 byte): 8 bits if the chksum_ena bit is set in the ctrl register (register 0x01, bit 4) 28 9116c?auto?11/10 atmel ata6870 [preliminary] figure 7-14. spi transaction fields organization note: 1. only send if chksum_ena bit set to 1 in the ctrl register 7.6.4.2 identification field atmel ata6870 chip identification the two chip identification bytes are sent over mosi to the atmel ? ata6870(n) in the chain. the ata6870(n) checks the lsb. when lsb=1, the information is for this device. the spi address will be decoded and the information proc essed. independent from this the identifica- tion bytes are shifted by one bit to the right and transferred to the next ata6870(n) in the chain. the 2 identification bytes allows th e identification of up to 16 ata6870s. . b yte5 to n-1 b yte n b yte4 b yte 3 b yte2 chipid0 control irqid0 chipid1 irqid1 chipid0 .... chk s um (1) data .... chk s um (1) data s pi write a cce ss s pi re a d a cce ss control irqid0 chipid1 irqid1 mi s o mo s i c s _n mi s o mo s i c s _n b yte1 29 9116c?auto?11/10 atmel ata6870 [preliminary] figure 7-15. identification field: chip-id reception 7.6.4.3 ata6870 irq identification figure 7-16. irq propagation scheme identification field 0x00 data control 0x04 0x00 c s _n ata 6 8 70 (2) mo s i_in ata 6 8 70 ( 3 ) mo s i_in ata 6 8 70 (n>4) mo s i_in ata 6 8 70 (4) mo s i_in ata 6 8 70 (1) mo s i_in ata 6 8 70 (4) identific a tion field h as l sb = 1 => decode s pi a cce ss . s hift it ? on the fly ? once to the right ata 6 8 70 (>4) identific a tion field h as l sb = 0 => device i s not a ffected. s hift it ? on the fly ? once to the right ata 6 8 70 (1-> 3 ) identific a tion field h as l sb = 0 => device i s not a ffected. s hift it ? on the fly ? once to the right data control 0x0 8 0x00 data control 0x00 0x00 data control 0x01 0x00 data control 0x02 ata 6 8 70 (n) ir q _int irq irq_in ata 6 8 70 (n-1) ir q _int irq irq_in mcu ata 6 8 70 (1) ir q _int irq irq_in 1 1 1 30 9116c?auto?11/10 atmel ata6870 [preliminary] ata6870(n) irq output is connected to ata6870(n-1) irq_in input. ata6870(n-1) irq output is a logic or between irq_in and its internal irq_int signal. ata6870(1) irq output is connected to mcu. figure 7-17. identification field: interrupt state emission with each spi access, a 16- bit irq state is send via miso synchronous to the identification field to the mcu with the interrupt state of all stacked atmel ata6870. the mcu, interrupted by an ata6870, has to send the identification fiel d to check the irq levels (in that case the checksum is not considered). it is also poss ible to continue the transaction with control and data field. the mcu decodes the identification field shifted in miso input. when bit m is set, ata6870(16-m) is requesting interrupt. figure 7-18. identification field m as ter s pi receive s identific a tion word = 0x2000 = 2 1 3 = 2 m . thi s me a n s ata 6 8 70 n u m b er (16-m = 16-1 3 ) = 3 h as irq pending. ata 6 8 70 ( 3 ) irq i s s et. => ata 6 8 70 ( 3 ) s et s the m s b of the fir s t b yte to b e s hifted o u t. other s b it s a re tho s e coming from u pper ata 6 8 70, s hifted once to the right. other s ata 6 8 70 s ass ert the m s b of the fir s t b yte to 0. other s b it s a re tho s e coming from u pper ata6 8 70, s hifted once to the right. 0x20 0x00 c s _n ata 6 8 70 (1) mi s o ata 6 8 70 (2) mi s o ata 6 8 70 (16) mi s o ata 6 8 70 ( 3 ) mi s o 0x00 0x00 0x 8 00x00 0x40 0x00 note: n = ic n u m b er 1 < = n < = 16 m = b it n u m b er 0 < = m < = 15 m = n -1 m(12) m(1 3 ) m(10) m(9) m( 3 ) m(1) m(2) m(6) m(4) m(5) m(7) m( 8 ) m(11) m(16) m(14) m(15) s ck mi s o mo s i c s _n i(1 3 ) i(12) i(15) i(16) i(14) i(9) i(11) i(10) i(5) i(4) i(7) i( 8 ) i(6) i(1) i( 3 ) i(2) 31 9116c?auto?11/10 atmel ata6870 [preliminary] 7.6.4.4 control field the control field defines the register to access and the direction (read/write). the size of the data (8, 16, or 112 bits) is defined by the address value in the control field. 7.6.4.5 data field the data field can be composed of 1, 2, or 14 bytes depending on the accessed register. irrespective of the data direction, a byte is always transmitted with msb first; a multi-byte word is transmitted with msbyte first. figure 7-19. control and data fields - 8-bits register write figure 7-20. control and data fields - 8-bits register read figure 7-21. control and data fields - 16-bits register write table 7-15. control field control field bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 a6 a5 a4 a3 a2 a1 a0 w/rd a(6) a(5) d a t a not relev a nt d a t a not relev a nt a(0) d(5) d(4) d( 3 ) d(2) d(1) d(0) d(7) d(6) 1 a(2) a(1) a(4) a( 3 ) s ck mi s o mo s i c s _n a(6) a(5) d a t a not relev a nt d a t a not relev a nt a(0) d(5) d(4) d( 3 ) d(2) d(1) d(0) d(7) d(6) 0 a(2) a(1) a(4) a( 3 ) s ck mi s o mo s i c s _n d a t a not relev a nt d a t a not relev a nt d a t a not relev a nt a(6) a(5) a(0) d(9) d( 8 ) d(7) d(6) d(5) d(2) d(1) d(0) d( 3 ) d(4) d(11) d(10) d(1 3 ) d(12) d(15) d(14) 1 a(2) a(1) a(4) a( 3 ) s ck mi s o mo s i c s _n 32 9116c?auto?11/10 atmel ata6870 [preliminary] figure 7-22. control and data fields - 16-bits register read in order to retrieve results from all channels in one atmel ? ata6870 without having to request for each channel, an spi 112-bit read-only "burst access" (datard16burst register; address = 0x7f) is implemented. when requested, the ata6870 outputs its 6 voltage channels v6 to v1 and one of the two temperature channels t2 and t1 in sequence on the spi bus. the dia- grams below show the control and data fields of such an access. figure 7-23. control and data fields - 112-bits register read d a t a not relev a nt a(6) a(5) a(0) d(9) d( 8 ) d(7) d(6) d(5) d(2) d(1) d(0) d( 3 ) d(4) d(11) d(10) d(1 3 ) d(12) d(15) d(14) 0 a(2) a(1) a(4) a( 3 ) s ck mi s o mo s i c s _n d a t a not relev a nt 11 1 d(9) d( 8 ) ch a nnel v6 d(7) d(6) d(5) d(2) d(1) d(0) d( 3 ) d(4) d(11) d(10) 00 00 0 11 11 s ck mi s o mo s i c s _n d(9) d( 8 ) d(7) d(6) d(5) d(2) d(1) d(0) d( 3 ) d(4) d(11) d(10) 00 00 s ck mi s o mo s i c s _n d(9) d( 8 ) d(7) d(6) d(5) d(2) d(1) d(0) d( 3 ) d(4) d(11) d(10) 00 00 s ck mi s o mo s i c s _n ch a nnel v1 ch a nnel temper a t u re t1 or t2 33 9116c?auto?11/10 atmel ata6870 [preliminary] one atmel ? ata6870 frame corresponds to the set of results obtained in one atmel ata6870. an atmel ata6870 frame is formatted as follows: figure 7-24. spi access to datard16burst register 0x7f when reading data of chained ata6870, data is transferred as follow: figure 7-25. example with two atmel ata6870 in a chain 7.6.4.6 communication error correct communication can be verified using various functions of the atmel ata6870. for internal synchronization, it is mandatory to keep clk running during any spi access; clk must be set on 4 clock cycles (at least) before spi access starts, and must be kept on 4 clock cycles (at least) after spi access ends up. keep ing at least 4 clk clock cycles between two consecutive spi accesses is mand atory. if this is not the ca se, the atmel ata6870s will detect an error in communication. the commerror bi t will be set in the status register 0x06). figure 7-26. spi access and clk activity the atmel ata6870 verifies that complete bytes (8bits long) are always transmitted. a transi- tion starts when cs_n goes to low and it ends when cs_n goes to high. the number of clock cycles (signal clk) is monitored during the tr ansition. this number of clock cycles has to be modulo 8. if the cs_n length is not modulo 8 clock cycles, the bit commerror is set in the sta- tus register. this will cause an interrupt to the mcu if the co mmerror is not masked by the commerrormsk bit in the irqmask register. adc 3 adc2 adct adc1 p a dding: 0x00 12- b it adc d a t a l sb m sb adc6 adc5 adc4 volt a ge ch a nnel s temp ch a nnel 16 b it 16 b it 16 b it 16 b it 16 b it 16 b it 16 b it s pi clock rd reg comm a nd chip1 ata 6 8 70 #1 fr a m e ata 6 8 70 #2 fr a me rd reg comm a nd chip2 s pi clock s ck mi s o mo s i c s _n clk off s pi acce ss s pi acce ss 4 clk_tick s 4 clk_tick s 4 clk tick s clk_off clk on 34 9116c?auto?11/10 atmel ata6870 [preliminary] 7.6.4.7 chksum field the atmel ? ata6870 provides the possibility of veri fying the transmitted data using a check- sum. setting chksum_ena bit to 1 in the ctrl r egister (default = 0) activates the checksum feature. the chksum field is an 8-bit checksum computed from the proceeding data (control and data fields, byte 3 to byte n-1). it is based on the polynomial x 8 +x 2 +x 1 +1. the way it is computed is depicted below: figure 7-27. lfsr-based checksum computation the checksum is calculated from the control fiel d and data field by a polynomial division. the data field can consist of 1 byte up to 14 bytes (112-bit read-only ?burst access?). the identification field (2 byte s) is not used to generate the checksum. the checksum is always sent by the microcontroller, independent of read write mode. the checksum is in the lfsr (linear feedback shift register) when the complete bitstream (the whole fields of the transaction) followed by 0x00 have been shifted in the lfsr. the checksum verification on the complete data transmission was ok when the complete bit- stream followed by the checksum have been shifted in the lfsr, and the content of the lfsr is 0x00. if this is not the case, the receiving at a6870 will set the chkerror bit in the status reg- ister. this will cause an interrup t to the mcu if the chkerror is not masked by the chkerrormsk bit in the irqmask register. see the example below. the checksum is serially computed from the 8-bit value 0x57. so the bitstream 0x5700 is shifted in the lfsr. the resulting checksum is [f6o, f6i, f5i ? f0i] at the last shift in cycle: table 7-16. checksum = [f6o, f6i, ... f0i] = 0xa2 input f01 f1i f2i f3i f4i f5i f6i f6o x00000000 5 d 000000000 110000000 001000000 110100000 7 d 001010000 110101000 111010100 111101010 0 d 001110101 011011010 001101101 011010110 f4i f5i f6o f6i f 3 i f2i f1i s eri a l b it s tre a m m s b fir s t f0i z -1 z -1 z -1 z -1 z -1 z -1 z -1 35 9116c?auto?11/10 atmel ata6870 [preliminary] during an spi write access, the checksum is computed by the mcu and sent msb first in the chksum field. for an spi read access, t he checksum is comput ed by the atmel ? ata6870 and is checked by the mcu. during chksu m, mcu has to send 0x00 on mosi, and must check that its own lfsr equals 0x00 at the end of chksum field. 7.6.4.8 device position for the atmel ata6870 (1), this is the device on the lowest level, the spi has to work as a standard logic cmos interface to the mcu. the spi?s between stacked ata6870 have to work as level-shifters based on current sour ces. these different phy sical interfaces can be selected by the pin mfirst. 0 d 001101011 011010101 010001010 001000101 0x2 0xa table 7-16. checksum = [f6o, f6i, ... f0i] = 0xa2 (continued) input f01 f1i f2i f3i f4i f5i f6i f6o x00000000 table 7-17. device position mfirst configuration 0 ata6870 (2) to ata6870 (n) 1 ata6870 (1) table 7-18. electrical characteristics no. parameters test conditions pin symbol min. typ. max. unit type* 12.1 high level input voltage mfirst mfirst 0.7 dvdd va 12.2 low level input voltage mfirst mfirst 0.3 dvdd va 12.3 hysteresis mfirst mfirst 0.05 dvdd vc 12.4 input current v mfirst = 0v to v dvdd mfirst mfirst ?1 +1 a a *) type means: a = 100% tested, b = 100% correlation te sted, c = characterized on samples, d = design parameter 36 9116c?auto?11/10 atmel ata6870 [preliminary] 7.6.5 digital inputs and outputs 7.6.5.1 digital output characteristics digital output characteristics (miso, irq) if the atmel ? ata6870 is configured as first ic (master) in a string (mfirst = 1), these pins are configured as an open drain output. if the ata6870 is configured to be a stacked ic (mfirst = 0), the output signals miso and irq coming from the upper ic need to be trans- ferred to the miso and irq outputs of the master in the string via the miso_in and irq_in inputs. in this case the miso and irq outputs act as level shifters based on current sources. digital output characteristics (mosi _out, sck_out, cs_n_out, clk_out) these outputs act as level shifters based on current sources. they transfer the input signals mosi_out, sck_out, cs_n_out, clk_out to the next ic above. if the ata6870 is the ic on the top level of a string, these outputs must be connected to vddhv. table 7-19. electrical characteristics no. parameters test conditions pin symbol min. typ. max. unit type* 13.1 low level output voltage i out = +5ma mfirst = 1 miso, irq v miso , v irq 0.2 vdd va 13.2 low level output current 0.3v, mfirst = 0 miso, irq i miso , i irq ?13 ?8 a a 13.3 high level output current 0.3v, mfirst = 0 miso, irq i miso , i irq ?65 ?40 a a *) type means: a = 100% tested, b = 100% correlation te sted, c = characterized on samples, d = design parameter table 7-20. electrical characteristics no. parameters test conditions pin symbol min. typ. max. unit type* 14.1 low level output current vddhv + 1v to vddhv + 2v (1) v (1) 25 55 a a 14.2 high level output current vddhv + 1v to vddhv + 2v (1) v (1) ?1 +1 a a *) type means: a = 100% tested, b = 100% correlation te sted, c = characterized on samples, d = design parameter note: 1. mosi_out, sck_out, cs_n_out, clk_out 37 9116c?auto?11/10 atmel ata6870 [preliminary] 7.6.5.2 digital input characteristics digital input characteristics (miso_in, irq_in) digital input characteristics (cs_n, sck, mosi, clk) table 7-21. electrical characteristics no. parameters test conditions pin symbol min. typ. max. unit type* 15.1 low level input current (vddhv + 1.4v) 0.3v miso_in, irq_in i miso_in i irq_in 13 a a 15.2 high level input current (vddhv + 1.4v) 0.3v miso_in, irq_in i miso_in i irq_in 40 a a *) type means: a = 100% tested, b = 100% correlation te sted, c = characterized on samples, d = design parameter table 7-22. electrical characteristics no. parameters test conditions pi n symbol min. typ. max. unit type* 16.1 high level input voltage mfirst = 1 (1) v (1) 0.7 dvdd dvdd v a 16.2 low level input voltage mfirst = 1 (1) v (1) 0.3 dvdd va 16.3 high level input current mfirst = 1 i (1) 50 100 a a 16.4 low level input current mfirst = 1 i (1) ?130 ?70 a a 16.5 low level input current mfirst = 0, v (1) = 1v to 2v (1) i (1) ?55 ?35 a a 16.6 high level input current mfirst = 0 v (1) = 1v to 2v (1) i (1) ?1 +1 a a *) type means: a = 100% tested, b = 100% correlation te sted, c = characterized on samples, d = design parameter note: 1. cs_n, sck, mosi, clk 38 9116c?auto?11/10 atmel ata6870 [preliminary] 7.6.5.3 test-mode pins the test-mode pins dtst, atst, pwtst (outputs) have to be kept open in the application. the test-mode pins scanmode and cs_fuse (inputs) have to be connected to vssa. these inputs have an internal pull-down resistor. the test-mode pin vddfuse is a supply pin. it must also be connected to vssa. 7.7 operations 7.7.1 voltage and temperature measurement at startup, the atmel ? ata6870 is supplied and is waiting for any operation request. the available operations are: ? 6 channels voltage acquisition with a temperature acquisition ? with voltage = v(mbat i+1 , mbat i ) (standard operation) and with voltage = v(temp1 or temp 2, tempvss) (sta ndard operation) ? with voltage = v(mbat i , mbat i ) (offset calibration: caloffset operation) and with voltage = v(tempvss, tempvss ) (offset calibra tion: caloffset operation) operation completion is flagged to the host mcu via the irq output in conjunction with datardy bit set in the status register. in order to retrieve the full results in a single access, the user has to access the datard16burst register (112bits). getting the results of a single chan- nel (voltage or temperature) is also possible. for this, first select the channel to read through the channelreadsel register, then retrieve the channel value through the datard16 register. it is not possible to order a new operation until the previous operation has been acknowl- edged. the host mcu acknowledges the interrupt by reading the status register. this resets the datardy bit as well as the irq output, and enables the ata6870 to start the next opera- tion. writing noop in the operation register during an operation running aborts the current operation. in this case, the datardy bit is not set and interrupt is not requested to the host mcu. the opstatus register flags whether operation is running, aborted, ended, or no opera- tion is running. table 7-23. input characteristics pins scanmode, cs_fuse, vddfuse no. parameters test conditions pi n symbol min. typ. max. unit type* 18.1 pull-down resistor scanmode, cs_fuse r scanmode , r cs_fuse 50 200 k a *) type means: a = 100% tested, b = 100% correlation te sted, c = characterized on samples, d = design parameter 39 9116c?auto?11/10 atmel ata6870 [preliminary] 7.7.2 discharge function each channel is independently dischargeable. discharge is activated or deactivated by the register channeldischsel. 7.7.3 low frequency timer function a low frequency timer (lft), sy nchronous to internal 50 khz o scillator provides the host mcu with a low power timer, which useful to either synchronize operations in the host mcu or mon- itor the atmel ? ata6870?s activity. the lft elapsing asserts an interrupt to the host mcu if the corresponding mask bit in the irq- mask register is not set. default is lft not enabled. to enable the lft, set the lftimer_ena bit to 1 in the ctrl register. lft counting time is fully programmable in the register lftimer. changing the lftimer register restarts the lft if the new counting time is smaller than the current value of the lft. otherwise, lft runs until it reaches the new end value. asserting lftrst bit in the rstr register resets and restarts the lft if the lft is enabled. oth- erwise, lft is reset but not started. each ata6870 will assert its own interrupt when the timer elapses. depending on how the timer is used, the host mcu may mask lftdone interrupts in the whole ata6870s chain, except the first one. as internal rc oscillators are not synchronized, this prevents the mcu from being interrupted each time one of the lft elapses. 7.7.4 undervoltage detection a programmable undervoltage detection function is embedded in the ata6870. after being digitalized, each of the 6 voltages is com pared to a programmable threshold defined in the udvthresh register. if one of the six channels is out of the range defined by the threshold, an interrupt is requested to the host mcu if the corresponding udv mask bit is not set in the irq- mask register. the default threshold is 1.5v. as soon as mcu has acknowledged, undervoltage information is no more available to mcu, because status register is cleared when mcu reads it out. as a consequence, the next under- voltage interrupt cannot occur until the atmel ata6870 leaves its current undervoltage state. 40 9116c?auto?11/10 atmel ata6870 [preliminary] 7.8 registers registers are read and written through the spi interface. table 7-24. register mapping register address control field read mode control field write mode register name access type function 0x00 0x00 - revid r 8 bits revision id/value mfirst, pow_on 0x01 0x02 0x03 ctrl rw 8 bits control register 0x02 0x04 0x05 operation rw 8 bits operation request 0x03 0x06 - opstatus r 8 bits operation status 0x04 - 0x09 rstr w 8 bits software reset 0x05 0x0a 0x0b irqmask rw 8 bits mask interrupt sources 0x06 0x0c - status r 8 bits status interrupt sources 0x08 0x10 - channeludvstatus r 8 bits channels undervoltage status 0x09 0x12 0x13 channeldischsel rw 8 bits select channel to discharge 0x0a 0x14 0x15 channelreadsel rw 8 bits select channel to read 0x0b 0x16 0x17 lftimer rw 8 bits low frequency timer control 0x0c 0x18 - calibstatus r 8 bits reserved 0x0d 0x1a 0x1b fusectrl rw 8 bits reserved 0x10 0x20 0x21 udvthresh rw 16 bits undervoltage detection threshold 0x11 0x22 - datard16 r 16 bits single access to selected channel value 0x12 0x24 0x25 ata6870test rw 16 bits reserved 0x7f 0xfe - datard16burst r 112 bits burst access to the whole channels (6 voltage and 1 temperature) 41 9116c?auto?11/10 atmel ata6870 [preliminary] 7.8.1 registers content 7.8.1.1 revid register 7.8.1.2 ctrl register 7.8.1.3 operation register table 7-25. revid register overview register revid address 0x00 reset value 0x02 7 (msb) 6 5 4 3 2 1 0 (lsb) x x x pow_en mfirst revid table 7-26. revid register content bit field description revid ata6870 revision number, revision b: 0x02 mfirst status input pin mfirst pow_en status input pin pow_en table 7-27. ctrl register overview register ctrl address 0x01 reset value 0x00 7 (msb) 6 5 4 3 2 1 0 (lsb) x x x chksum_ena lftimer_ena tfmode_ena x x table 7-28. ctrl register content bit field description tfmode_ena 0: prevent ata6870 to switch to test mode 1: not allowed for customer use lftimer_ena 0: disable internal low frequency timer 1: enable internal low frequency timer chksum_ena 0: disable spi transaction checksum computation/check 1: enable spi transaction checksum computation/check table 7-29. operation register overview register operation address 0x02 reset value 0x02 7 (msb) 6 5 4 3 2 1 0 (lsb) x x opmode tempmode voltmode oprqst 42 9116c?auto?11/10 atmel ata6870 [preliminary] when a conversion operation is finished and the interrupt has been acknowledged by the mcu the operation register is automatically reset to ?noop?. writing ?noop? in the register when conversion operation is running, aborts the current operation. other changes are not accepted during any operation. figure 7-28. typical data acquisition flow table 7-30. operation register content bit field description oprqst 0: noop: no operation, or abort current operation 1: acqrqst: start the analog to digital conversion an interrupt is generated when data is available in datard16/datard16burst. voltmode 00: caloffset: select v(mbat(i), mbat(i)) as input of voltage channels. (offset calibration) 01: acqv: select v(mbat(i+1), mbat(i)) as input of voltage channels (default) 10: not allowed te m p m o d e 0: select temp1 input pin as input of temperature channel 1: select temp2 input pin as input of temperature channel opmode 00: 6 voltage channels and temperature acquisition 01: 6 voltage channels acquisition only 1x: temperature acquisition only conver s ion fini s hed op s t a t us = re su lt av a il ab le s t a t us = d a t a re a dy irq data rdy a s ic 3 re a d/check op s t a t us re a d/check s t a t us a s ic2 re a d/check op s t a t us re a d/check s t a t us a s ic1 re a d/check op s t a t us re a d/check s t a t us a s ic1 (mfir s t = 1) mcu s et oper a tion = acq * /cal * ... ... a s ic 3 b u r s t re a d d a t a a s ic2 b u r s t re a d d a t a a s ic1 b u r s t re a d d a t a b a ckgro u nd t as k s /idle r u n s conver s ion op s t a t us = r u nning init s t a te op s t a t us = noop s t a t us cle a red op s t a t us = noop irq acknowledged s t a t us cle a red conver s ion fini s hed op s t a t us = re su lt av a il ab le s t a t us = d a t a re a dy irq data rdy a s ic2 (mfir s t = 0) r u n s conver s ion op s t a t us = r u nning op s t a t us = noop s t a t us cle a red op s t a t us = noop s t a t us cle a red init s t a te op s t a t us = noop s t a t us cle a red conver s ion fini s hed op s t a t us = re su lt av a il ab le s t a t us = d a t a re a dy irq data rdy a s ic 3 (mfir s t = 0) r u n s conver s ion op s t a t us = r u nning init s t a te op s t a t us = noop s t a t us cle a red 43 9116c?auto?11/10 atmel ata6870 [preliminary] 7.8.1.4 opstatus register figure 7-29. operation status register management the opstatus register is reset when read after a completed or aborted operation. reading the register before starting an operation is not mandatory. reading data conversion results or reading the opstatus register during an operation does not affect the opstatus register. table 7-31. opstatus register overview register opstatus address 0x03 reset value 0x00 7 (msb) 6 5 4 3 2 1 0 (lsb) x x x x x x opstatus table 7-32. opstatus register content bit field description opstatus 00: no operation 01: operation is ongoing 10: operation is finished, result is available 11: operation is cancelled, result is not available oper a tion fini s hed, re su lt av a il ab le oper a tion a b orted, re su lt not av a il ab le oper a tion r u nning end of conver s ion u s er s progr a m s noop s t a t us reg h as b een re a d a nd: u s er progr a m s conver s ion oper a tion or re a d s oper a tion s t a t us regi s ter u s er progr a m s conver s ion oper a tion or re a d s oper a tion s t a t us regi s ter u s er s progr a m s conver s ion s oper a tion u s er re a d s oper a tion s t a t us regi s ter, re s et no op 44 9116c?auto?11/10 atmel ata6870 [preliminary] 7.8.1.5 rstr register lftrst resets and restarts the low frequency timer if not disabled (lftimer_ena = 0). 7.8.1.6 irqmask register table 7-33. rstr register overview register rstr address 0x04 reset value 0x00 7 (msb) 6 5 4 3 2 1 0 (lsb) x x x x x x lftrst 0 table 7-34. rstr register content bit field description lftrst 0: no reset 1: low frequency timer software reset table 7-35. irqmask register overview register irqmask address 0x05 reset value 0x00 7 (msb) 6 5 4 3 2 1 0 (lsb) x x x chkerrormask udvmask commerrormask lftdonemask datadrymask table 7-36. irqmask register content bit field description datardymask mask data ready interrupt when set to 1 wakeupmask mask lftdone interrupt when set to 1 commerrormask mask commerror interrupt when set to 1 udvmask mask undervoltage detection interrupt when set to 1 chkerrormask mask checksum error interrupt when set to 1 45 9116c?auto?11/10 atmel ata6870 [preliminary] 7.8.1.7 status register any bit among {datardy, lftdone, commerror, udv, chkerror} set in the status register requests an interrupt to the external mcu if the corresponding mask bit in the irqmask register is 0. reading the status register acknowledges the interrupt and resets its content. por and tfmdeon cause no interrupt. table 7-37. status register overview register status address 0x06 reset value 0x10 7 (msb) 6 5 4 3 2 1 0 (lsb) x tfmdeon por chkerror udv commerror lftdone datardy table 7-38. status register content bit field description datardy conversion finished lftdone low frequency timer elapsed commerror bad spi comman d detected (wrong length) udv undervoltage detected chkerror error on checksum check por power on reset detected tfmdeon test mode on 46 9116c?auto?11/10 atmel ata6870 [preliminary] 7.8.1.8 channeludvstatus register undervoltage is detected when voltage decreases under the threshold value defined in udvthresh register. when undervoltage is detected on a channel, the atmel ? ata6870 requests an interrupt if the udvmask bit in the irqmask register is 0. table 7-39. channeludvstatus register overview register channeludvstatus address 0x08 reset value 0x00 7 (msb) 6 5 4 3 2 1 0 (lsb) x x chudv6_stat chudv5_stat chudv4_stat chudv3_stat chudv2_stat chudv1_stat table 7-40. channeludvstatus register content bit field description chudv1_stat 1: undervoltage detected on channel 1 0: no undervoltage detected on channel 1 chudv2_stat 1: undervoltage detected on channel 2 0: no undervoltage detected on channel 2 chudv3_stat 1: undervoltage detected on channel 3 0: no undervoltage detected on channel 3 chudv4_stat 1: undervoltage detected on channel 4 0: no undervoltage detected on channel 4 chudv5_stat 1: undervoltage detected on channel 5 0: no undervoltage detected on channel 5 chudv6_stat 1: undervoltage detected on channel 6 0: no undervoltage detected on channel 6 47 9116c?auto?11/10 atmel ata6870 [preliminary] 7.8.1.9 channeldischsel register the channels are dischargeable simultaneously. 7.8.1.10 channelreadsel register table 7-41. channeldischsel register overview register channeldischsel address 0x09 reset value 0x00 7 (msb) 6 5 4 3 2 1 0 (lsb) x x chv6_disch chv5_disch chv4_disch chv3_disch chv2_disch chv1_disch table 7-42. channeldischsel register content bit field description chv1_disch 1: enable voltage channel 1 discharge 0: disable voltage channel 1 discharge chv2_disch 1: enable voltage channel 2 discharge 0: disable voltage channel 2 discharge chv3_disch 1: enable voltage channel 3 discharge 0: disable voltage channel 3 discharge chv4_disch 1: enable voltage channel 4 discharge 0: disable voltage channel 4 discharge chv5_disch 1: enable voltage channel 5 discharge 0: disable voltage channel 5 discharge chv6_disch 1: enable voltage channel 6 discharge 0: disable voltage channel 6 discharge table 7-43. channelreadsel register overview register channelreadsel address 0x0a reset value 0x00 7 (msb) 6 5 4 3 2 1 0 (lsb) channelreadsel 48 9116c?auto?11/10 atmel ata6870 [preliminary] this register can be used to quickly read a single channel without using a full burst access. the value of the selected channe l will be available in the datard16 register. the value will always be updated by writing a channel address to the channelreadsel register. data in this register is not valid during ongoing data conversion. 7.8.1.11 lftimer register the default timer value is 59.965s (0xf9) for f osc =50khz. figure 7-30. block diagram lftimer formula for delay time calculation: table 7-44. channelreadsel register content bit field description channelreadsel 111: value of the lft is returned in datard16 register 110: temperature channel available in datard16 register 101: voltage channel6, value available in datard16 register 100: voltage channel5, value available in datard16 register 011: voltage channel4, value available in datard16 register 010: voltage channel3, value available in datard16 register 001: voltage channel2, value available in datard16 register 000: voltage channel1, value available in datard16 register lftimer register overview register lftimer address 0x0b reset value 0xf9 7 (msb) 6 5 4 3 2 1 0 (lsb) lftprescaler lftdelay table 7-45. lftimer register content bit field description lftdelay contains the present low frequency timer delay value lftprescaler 0: prescalervalue = 1 1: prescalervalue = 6 7- b it co u nter del a y time el a p s ed comp lftpre s c a ler lftdel a y /6 /4096 50 khz cle a r delay time 1 t osc [hz] ------------------------ - 4096 6 lftprescaler d () lftdelay d 1 + () = 49 9116c?auto?11/10 atmel ata6870 [preliminary] the lft can be programmed to the following values (f osc =50khz): lftprescaler = 0: 0.082s <= duration <= 10.486s, increment = 82ms lftprescaler = 1: 492 ms <= duration <= 62.915s, increment = 492ms when lft elapsed, an interrupt is requested unl ess lftdonemask bit is set in the irqmask register. for details on the tolerances for the oscillator, see section 7.5.6 ?rc osc illator? on page 25 . keeping at list 100 s between two successive lftimer register write accesses prevents inter- nal metastability issues, which might result in bad l ftdelay decoding. 7.8.1.12 test-mode register test-mode registers 1, 2, and 3 are reserved for the factory calibration process. they are not allowed for customer use. table 7-46. test-mode register 1 overview register testmode1 address 0x0c reset value 0x03 7 (msb) 6 5 4 3 2 1 0 (lsb) 00000011 table 7-47. test-mode register 2 overview register testmode2 address 0x0d reset value 0x07 7 (msb) 6 5 4 3 2 1 0 (lsb) 00000111 table 7-48. test-mode register 3 overview register udvthresh address 0x12 reset value 0x0e00 1514131211109876543210 0000011110000000 50 9116c?auto?11/10 atmel ata6870 [preliminary] 7.8.1.13 udvthresh register default value is 1.5v (0x0570, 1392 d ) 1.5v = vref (1392 ? 410) / (1502 ? 410) see also section 7.5.1.2 ?12 bits incremental adc? on page 19 . 7.8.1.14 datard16 register table 7-49. udvthresh register overview register udvthresh address 0x10 reset value 0x0570 1514131211109876543210 xxxx udvthresh table 7-50. udvthresh register content bit field format description udvthresh 12 bits threshold for undervoltage detection table 7-51. datard16 register overview register datard16 address 0x11 reset value 0x0000 1514131211109876543210 xxxx datard16 table 7-52. datard16 register content bit field format description datard16 12 bits return selected channel value (see section 7.8.1.10 ?channelreadsel register? on page 47 ) 51 9116c?auto?11/10 atmel ata6870 [preliminary] 7.8.1.15 datard16burst register table 7-53. datard16burst register overview register datard16burst address 0x7f reset value 0x0000 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 96 x x x x channel6 data 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 x x x x channel5 data 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 x x x x channel4 data 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 x x x x channel3 data 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 x x x x channel2 data 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 x x x x channel1 data 1514131211109876543210 x x x x temperature data table 7-54. datard16burst register content bit field format description datard16burst 112bits returns the values of all channels from one ata6870 , including temperature measurement 52 9116c?auto?11/10 atmel ata6870 [preliminary] figure 7-31. application figure 7-31 shows an application with 2 stacked atmel ? ata6870s. mbat6 c s _n clk s ck mo s i mi s o mfir s t dt s t s canmode c s _fu s e dv ss vddfu s e dvdd di s ch6 1k 1.5k 1k 1k 1k 1k 1k 121k 1k 10nf 33 f 220nf 100nf 100nf 100nf 100nf 100nf 100nf + 10 mbat5 di s ch5 100nf 100nf 100nf 100nf 100nf 100nf 33 f 220nf + mbat7 vddhv irq_in clk_out c s _n_out s ck_out mo s i_out mi s o_in pd_n vddhvp mbat 3 mbat4 di s ch4 di s ch 3 mbat2 ntc ntc di s ch2 ata6 8 70 ata6 8 70 mbat1 10 irq di s ch1 vddhvm pow_ena pd_n_out temp2 bia s re s at s t pwt s t tempvref tempv ss temp1 gnd avdd av ss mbat6 c s _n clk s ck mo s i mi s o mfir s t dt s t s canmode c s _fu s e dv ss vddfu s e dvdd di s ch6 1k 1k 1k 1k 1k 1k 121k 1k 10nf mbat5 di s ch5 mbat7 vddhv irq_in clk_out c s _n_out s ck_out mo s i_out mi s o_in pd_n vddhvp mbat 3 mbat4 di s ch4 di s ch 3 mbat2 ntc ntc di s ch2 mbat1 10 irq di s ch1 vddhvm pow_ena pd_n_out temp2 c s n s ck mo s i mi s o out irq vdd micro- controller gnd clk bia s re s at s t pwt s t tempvref tempv ss temp1 gnd avdd av ss 10 10 f 100nf + 10 f 100nf + 53 9116c?auto?11/10 atmel ata6870 [preliminary] 9. package information 9.1 markings as a minimum, the devices will be marked with the following: ? date code (year and week number) ?atmel ? part number (ata6870) 8. ordering information extended type number package moq ATA6870-PLPW qfn48, 7 7 1,000 pieces ata6870-plqw qfn48, 7 7 4,000 pieces specifications according to din technical drawings issue: 1; 21.03.06 drawing-no.: 6.543-5130.01-4 0.5 nom. 5.5 24 13 37 48 36 25 1 12 z 5.6 0.15 bottom 7 48 1 12 pin 1 identification top package: vqfn_7 x 7_48l exposed pad 5.6 x 5.6 dimensions in mm not indicated tolerances 0.05 0.2 0.9 0.1 0.4 0.1 z 10:1 0.23 0.07 54 9116c?auto?11/10 atmel ata6870 [preliminary] 10. revision history please note that the following page numbers referred to in this section refer to the specific revision mentioned, not to this document. revision no. history 9116c-auto-11/10 ? figure 7-1 ?power-down? on page 10 changed. ? figure 7-7 ?block diagram battery voltage measurement? on page 18 changed ? table 7-6 ?inputs of the multiplexer? on page 18 changed ? adc adjustment + procedur e on pages 19 to 21 changed: - section 7.5.1.2 ?12 bits increment al adc? on pages 19 to 21 changed ? table 7-11 ?electrical characteristics? number 7.5 on page 23 changed ? section 7.7.1 ?voltage and temper ature measurement? on page 38 changed ? table 7-32 ?operation register content? on page 42 changed ? figure 7-31 ?application? on page 52 changed 9116b-auto-10/09 ? table 3-1 ?pin description? on page 4 changed ? table 5 ?abs.max.ratings? changed ? table 7-1 ?electrical characteristics? on page 11 changed ? table 7-5 ?electrical characteristics? on page 16 changed ? table 7-7 ?electrical characteristics? on page 19 changed ? table 7-9 on page 21 changed ? table 7-11 ?battery cell temperat ure measuring characteristics? on page 23 changed ? table 7-12 ?battery cell temperat ure measuring characteristics? on page 24 changed ? section 7.5.7 ?power on reset? on page 25 changed ? table 7.15 ?battery cell temperatur e measuring characteristics? on page 25 changed ? figure 7-13 ?host interface? on page 26 changed ? figure 7-14 ?spi transaction field organization? on page 28 changed ? section 7.6.4.7 ?chksum field? on page 34 changed ? table 7-19 ?electrical characteristics? on page 35 changed ? table 7-22 ?electrical characteristics? on page 37 changed ? table 7-23 ?electrical characteristics? on page 37 changed ? table 7-26 ?register mapping? on page 40 changed ? table 7-32 ?operation register content? on page 42 changed ? section 7.8.1.5 ?rstr register? on page 44 changed ? table 7.55 ?datard16burst register overview? on page 51 changed ? figure 7-31 ?application? on page 52 changed atmel corporation 2325 orchard parkway san jose, ca 95131 usa tel: (+1)(408) 441-0311 fax: (+1)(408) 487-2600 atmel asia limited unit 01-5 & 16, 19/f bea tower, millennium city 5 418 kwun tong road kwun tong, kowloon hong kong tel: (+852) 2245-6100 fax: (+852) 2722-1369 atmel munich gmbh business campus parkring 4 d-85748 garching b. munich germany tel: (+49) 89-31970-0 fax: (+49) 89-3194621 atmel japan 9f, tonetsu shinkawa bldg. 1-24-8 shinkawa chuo-ku, tokyo 104-0033 japan tel: (+81) (3) 3523-3551 fax: (+81) (3) 3523-7581 ? 2010 atmel corporation. all rights reserved. / rev.: 9116c?auto?11/10 atmel ? , logo and combinations thereof, and others are registered trademarks or trademarks of atmel corpor ation or its subsidiaries. o ther terms and product names may be trademarks of others. disclaimer: the information in this document is provided in con nection with atmel products. no license, express or implied, by estoppel or otherwise, to any intellec- tual property right is granted by this document or in connection with the sale of atmel products. except as set forth in the at mel terms and conditions of sales located on the atmel website, atmel assumes no liability whatsoever and disclaims any express, implied or statutory warranty relating to its products including, but not limited to, the implied warranty of merchantability, fitness for a particu - lar purpose, or non-infringement. in no event shall atmel be liable for any direct, indirect, consequential, punitive, special or incidental damages (including, without limitation, damages for lo ss and profits, business interruption, or loss of information) arising out of the use or inabil ity to use this document, even if atmel has been advised of the possibility of such damages. at mel makes no representations or warranties with respect to the accura cy or completeness of the contents of this document and reserv es the right to make changes to specifications and products descriptions at any time without not ice. atmel does not make any commitment to update the informati on contained herein. unless specif- ically provided otherwise, atmel produc ts are not suitable for, and shall not be used in, automotive applications. atmel produc ts are not intended, authorized, or war- ranted for use as components in applicatio ns intended to support or sustain life. |
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